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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">TRCSTALLCTLR, Stall Control Register</h1><p>The TRCSTALLCTLR characteristics are:</p><h2>Purpose</h2>
        <p>Enables trace unit functionality that prevents trace unit buffer overflows.</p>
      <h2>Configuration</h2><p>External register TRCSTALLCTLR bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-trcstallctlr.html">TRCSTALLCTLR[31:0]</a>.</p><p>This register is present only when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented and TRCIDR3.STALLCTL == 1. Otherwise, direct accesses to TRCSTALLCTLR are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>TRCSTALLCTLR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="18"><a href="#fieldset_0-31_14">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-13_13-1">NOOVERFLOW</a></td><td class="lr" colspan="4"><a href="#fieldset_0-12_9">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-8_8">ISTALL</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">LEVEL</a></td></tr></tbody></table><h4 id="fieldset_0-31_14">Bits [31:14]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-13_13-1">NOOVERFLOW, bit [13]<span class="condition"><br/>When TRCIDR3.NOOVERFLOW == 1:
                        </span></h4><div class="field">
      <p>Trace overflow prevention.</p>
    <table class="valuetable"><tr><th>NOOVERFLOW</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Trace unit buffer overflow prevention is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Trace unit buffer overflow prevention is enabled.</p>
        </td></tr></table>
      <p>Note that enabling this feature might cause a significant performance impact.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-13_13-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-12_9">Bits [12:9]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-8_8">ISTALL, bit [8]</h4><div class="field">
      <p>Instruction stall control. Controls if a trace unit can stall the PE when the trace buffer space is less than LEVEL.</p>
    <table class="valuetable"><tr><th>ISTALL</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The trace unit must not stall the PE.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The trace unit can stall the PE.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-7_4">Bits [7:4]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-3_0">LEVEL, bits [3:0]</h4><div class="field"><p>Threshold level field. The field can support 16 monotonic levels from <span class="binarynumber">0b0000</span> to <span class="binarynumber">0b1111</span>.</p>
<p>The value <span class="binarynumber">0b0000</span> defines the Minimal invasion level. This setting has a greater risk of a trace unit buffer overflow.</p>
<p>The value <span class="binarynumber">0b1111</span> defines the Maximum invasion level. This setting has a reduced risk of a trace unit buffer overflow.</p><p>Note that for some implementations, invasion might occur at the minimal invasion level.</p>
<p>One or more of the least significant bits of LEVEL are permitted to be <span class="arm-defined-word">RES0</span>. Arm recommends that LEVEL[3:2] are fully implemented. Arm strongly recommends that LEVEL[3] is always implemented. If one or more bits are <span class="arm-defined-word">RES0</span> and are written with a nonzero value, the effective value of LEVEL is rounded down to the nearest power of 2 value which has the <span class="arm-defined-word">RES0</span> bits as zero. For example, if LEVEL[1:0] are <span class="arm-defined-word">RES0</span> and a value of <span class="binarynumber">0b1110</span> is written to LEVEL, the effective value of LEVEL is <span class="binarynumber">0b1100</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing TRCSTALLCTLR</h2>
        <p>Must be programmed if implemented.</p>

      
        <p>Writes are <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> if the trace unit is not in the Idle state.</p>
      <h4>TRCSTALLCTLR can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>ETE</td><td><span class="hexnumber">0x02C</span></td><td>TRCSTALLCTLR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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